Binary counter and logic gates for providing traffic flow condition for two successive binary counts

ABSTRACT

A three-stage binary counter establishes six different traffic flow conditions without feedback connections by using logical circuitry to maintain two of the traffic conditions for two successive binary counts.

United States Patent [72] Inventor [2i Appl. No. [22] Filed [45 Patented (73 Assignee Philip Cane Brooklyn. N.Y. 1 31,823 Apr. 29, 1970 Aug. 3, 1971 The Marbelitc Company, Inc. Brooklyn, N.Y. Continuation 0! application Ser. No. 532,520, Feb. 21, i966.

(54] BINARY COUNTER AND LOGIC GATES FOR PROVIDING TRAFFIC FLOW CONDITION FOR I TWO SUCCESSIVE BINARY COUNTS 3 China, 8 Drawing Figs. [52] US. I 307/220, 307/224, 328/46, 328/48 [51] Int. I03k 21/00, H03k 23/08 [50] Field of Search 307/220.

[56] References Cited UNITED STATES PATENTS 3,04 l ,477 6/l962 Budts et a]. 307/291 X 3,267,424 8/l966 Brockett et al. 340/37 3,28 L782 WI 1966 Frielinghaus 340/41 3,286,230 I ll i966 Bolton 340/44 X 2,771,551 ll/l956 Hampton 328/48 X OTHER REFERENCES Pub. I, Pulse, Digital, and Switching Waveforms" by Millman and Taub, pages 678 to 680, dated 1955.

Primary Examiner-Stanley D. Miller, Jr. Attorney-Wolf, Greenfield and Sacks ABSTRACT: A three-stage binary counter establishes six different traffic flow conditions without feedback connections by using logical circuitry to maintain two of the traffic conditions for two successive binary counts.

CODE GATE All FIERSI REL DRIVEB II I! III I III lllll m Ill-l4 II I l I II 2 L PED MEMORY 8| TIMING CIRCUIT SHEET 2 (IF 5 PATENIED AUG 3 Ian INVENTOR PHILIP CANE PATENT ATTORNEY ZZW@/ /L FIG. 2

MANUAL PEDESTRIAN PUSHBUTTON COORDINATION CONTROL (J/C CONTROL 2 OFF I I I I I I I I I MANUAL SWITCH PATENTED AUG 319m SHEET 5 BF 5 WV l MINIMUM REST llllllllllllll ALL RED WALK 27 5WALK CLEARANCE P-DS3 P-D3 P-R9 RECALL P-Rl2 P-DS5 PED. CALL FIG.

CONTROL PANEE WALK .E RN 0A MC EW Vl. .mH P

Y B M K n R m RH OEN RW T E E D E BT RA R R MN w WA R G A0 PF P D r (w q felv A B A 3 3 K K P E N A P A 2 B M K 2 L I'K V E I l I 0 l I 1.. R m

POWER SOURCE PATENT ATTORNEY FIG. 6

BINARY COUNTER AND LOGIC GATES FOR PROVIDING TRAFFIC FLOW CONDITION FOR TWO SUCCESSIVE BINARY COUNTS This application IS a continuation of applicant's copending application Ser No 532,520 filed In the LES. Pat. Office Feb. 21, I966.

This invention relates to traffic control devices. subject to pedestrian actuation, to enable pedestrians to initiate a signal sequence which is intended to stop the vehicular traffic so that pedestrians can safely cross the street. Tratfic signal indications may simultaneously provide the pedestrians with signal information intended to inform them when it is safe or unsafe for them to cross the through street. In the usual application, the combination of signals and control device is located approximately midway between street intersections and the controller will be referred to as a midintersection controller.

The invention, unlike those predominate in the art, employs no electromechanical devices except for the relays used to carry the signal light loads and the flasher to cause a flashing DON'T WALK signal. The entire controller involving all control functions may be readily and economically constructed of solid-state electronic components which are readily available and reasonably priced. The use of these components in the circuits to be described results in a traffic signal controller with no moving parts, with high reliability, requiring virtually no maintenance, impervious to the temperature extremes met in the usual applications and subject to economical production.

The usual application of this invention utilizes a standard RED, AMBER OR YELLOW, AND GREEN signal for the guidance of the motorist and a WALK-DON'T WALK signal for the guidance of the pedestrian. The signal lights will ordinarily display GREEN to the motorist and 'DONT WALK to the pedestrian. Upon actuation of a push button by the pedestrian, the controller will react to change the signalsin the following sequence:

III

dition. The controller counter will again remain at rest until a subsequent pedestrian pushbutton actuation is registered.

For further comprehension of the invention and of the obects and advantages thereof, reference will be had to the following description, the accompanying drawings and to the appended claims in which the novel features of the invention are more particularly set forth. The preferred embodiment of the invention will be described with reference to the following drawings in which like parts and interconnected terminal points are so designated and carried throughout the drawings.

FIG. 1 of the drawings is a block diagram of the midintersection controller, showing the basictfunctional modules of the controller as well as-the interrelations between these functional modules. In this figure the numbers inside the box designate the figure where the module is shown in detail.

FIG. 2 shows detailed electronics of the pedestrian memory circuitry and the timing circuitry. The pedestrian memory circuitry records the actuation of a push button, or similar device by the pedestrian. The timing circuitry, associated with the timing potentiometers of (FIG. 5) control panel, controls the timing of the periodsof signal display. All electronic components located in FIG. 2 are designated with the prefix T.

FIG. 3 includes the electronics of the counter which responds, in a sequential fashion, to impulses received from the timing circuitry of the FIG. 2. All electronic components located in FIG. 3 are designated with the prefix C.

FIG. 3A is a tabulated listing of the counter output conditions for each of the eight positions of the counter. The headings FF-l, FF-2, FF-3 refer to the three stages of the binary counter, in which the output is designated as either 0 or 1.

FIG. 4 shows the code gate circuitry used to enable the counter to provide outputs such that each counter position is enabledto energize an associated timing control potentiometer of FIG. 5. In addition, amplifying devices are driven so that output relays shown in FIG. 6 may be selectively, individually or concurrently energized. All electronic components located Period 1 2 3 4 5 6 1 Vehicular direction Green Green. Amber Red Red- Red Green.

Pedestrian direction Don't walk. Don't walk. Don't walk. Don't walk. Walk Flgshiitig, m Don't walk.

on wa Each of the periods except four Don't Walk, period 2, is separately, adjustably timed. Period 2 is untimed and is of indefinite length in the absence of pedestrian actuation. Provision for interrelated operation of the controllers is included. With this provision the instant of leaving period 2 is controllable. Thus controllers located at midintersection points maybe coordinated with adjacent intersection controllers or with other midintersection controllers to avoid random stoppage of vehicular traffic.

In general, the operation of the controller results from the actuation of a push button. The push button operation sets up a memory" circuit, which in conjunction with a coordinated circuit, energizes a short-timing circuit when REST condition is reached. This timing circuit, acting through an amplifier, causes a three-stage binary counting circuit to change from its static REST POSITION. Each subsequent position of the counter, through the use of "AND" gate circuitry, connects individual variable (timing) resistors to charge a timing capacitor. When the capacitor voltage reaches a definite predetermined value, the timing amplifier reacts to advance the counter through an additional position. At the instant of counter change, a resetting voltage is returned to discharge the timing capacitor and thus ready it for the next timing period. In each of the counter positions, the "AND" gates in addition to energizing the timing resistors, act through OR" circuits to control lamp-load carrying relays and hence control the signal display. A voltage from the gate defining the WALK position restores the memory circuit to the nonactuated conin FIG. 4 are designated with the prefix G.

FIG. 5 shows the control panel which includes some control and indicating devices. The timing for each of the periods is controlled by means of variable resistors. The indicator lights show which of the periods is in effect. All electronic components located in FIG.5 are designated with the prefix P.

FIG. 6 shows how the output relays are interconnected to provide the signal sequence desired. Components located in FIG. 6 are relays which are designated with the letter K.

FIG. 6A tabulates the signal indications resulting from the individual or combined energization of the output relays.

In the drawings and in the specifications, which here follow, like numerals indicate similar elements. Furthermore, the letter immediately preceding the numeral indicates the type of element. Thus, C-R 26 indicates: C in counter (FIG. 3), R a resistor and 26, the resistor numbered 26. The element identification is as follows: Q transistor, D diode, R resistor, C capacitor, K relay, D S indicator signal and SW switch.

The circuitry and method employed to energize the signal lights will-be explained to facilitate understanding of the total operationof the controller. When relays K 1, K 2 and K 3 (FIG. 6) are unenergized (the condition shown in FIG. 6),the signal lights displayed are RED and DONt WALK. The circuit may be traced from the power source terminal through the center contact ofK l B to the bottom contact of K I B and thence to the red signal. Similarly, the power source is fed to the bottom contact of K 3 B thence to the center contact of K 3 B, to the DONT WALK signal.

In sequence. as listed in FIG. 6A. the relay and light conditions are as follows: When K 1 and K 2 are energized. the DON'T WALK signal is energized through K 3 B as before. The GREEN signal is energized from the power source to the center contact of K 1 B, to the top contact of K I B, to the center contact of K 2 B, to the top contact of K 2 B and thence to the GREEN signal terminal.

When K I alone is energized, the DONT WALK signal is energized through K 3 B as previously described. The AMBER signal is energized from the power source to the center contact of K I B to the top contact of K 1 B, to the center contact of K 2 B, to the bottom contact of K 2 B. to the AMBER signal.

When K I, K 2 and K 3 are energized, the circuit conditions lead to RED and DONT WALK signal illumination.

When K 2 and K 3 are energized, the WALK signal is energized from the power source to the center contact K 1 A to the bottom contact K 1 A to the center contact K 2 A, to the top contact K 2 A, to the center contact K 3 A. to the WALK signal terminal. The RED signal is energized from the power source to the center contact of K 1 B to the bottom contact of K 1 B to the RED signal terminal.

When K 3 is energized, the energy from a pulsing or flashing source is fed from the top contact of K 3 B to the center contact of K 3 B, to the DON'T WALK terminal, to provide a flashing DON'T WALK signal. The RED signal is energized from the power source to the center contact of K 1 B to the bottom contact ofK 1 B to the RED signal terminal. As will be further explained, the relays, K 1, K 2 and K 3, are energized by means of transistors G-Q 3, G-Q 2 and G-Q 1 (see FIG. 4). The controller is designed to provide selective operation of transistors G-Q 3, 6-0 2 and G-Q 1 as a result of the circuit logic, and the various input control signals. In order to better understand the operation of the controller, the several circuit subsections will be explained in detail and the interrelations between the circuits will be established.

The electronics requires several DC voltages to operate properly. These are derived from conventional rectifier, regulator and filter circuits, which require no description, since they are well known in the art. The voltages will be referred to as 6 v., +l7 v., +22 v., and +27 v., which approximate the voltage levels used in one embodiment but which are not critical since by a different selection of components a different group of values might be used. Throughout this description, these voltages will be referred to by values indicated for convenience.

Transistors, C- 1 and GO 2 (see FIG. 3) form a monostable multivibrator. In addition, there is a three-stage binary counter consisting of transistors C-Q 8 and GO 7 as the first stage, C-Q 6 and GO 5 as the second stage, and C-Q 4 and C- Q 3 as the third stage. Each of these stages forms a bistable multivibrator (flip-flop) in which in each stage either of the transistors is able to conduct with the other nonconducting (cutoff).

Assume C-0 8 is conducting; the path ofconduction will be from the +22 v. through resistor C-R 17, through resistor C-R 32 through the collector emitter path of C-Q 8, through resistor C-R 31 to the 6 v. source. Since O0 8 is in conduction, there will be a large voltage drop through C-R 32 and the voltage at the junction of C-R 27 and C-R 32 will be very low. The current drive to the base of C-0 7 will consequently not be available and C-0 7 will be nonconducting. As a result, there will be a drive from the +22 v. source through OR 18, OR 30 and C-R 28 to the base of CC) 8, causing C-0 8 to be held in the conducting condition. Transistor C-Q 8 will conduct and CO 7 will be nonconducting until a negative pulse is applied to the junction of capacitors CC 13 and CC 12. The negative going pulse, as will be shown, is obtained from the junction ofCR 7 and C-C 2. The negative pulse applied to the junction of CC 12 and C-C 13 is applied to the base of C-Q 7 through C-D 7 and to the base of GO 8 thru C-D 8. Since C-0 7 is already cutoff, no change in the condition of C-Q 7 can be made. The negative pulse is applied to the base of C-0 8 and to the collector of GO 7 through CR 26. The negative pulse at the base of C-Q 8 causes C-Q 8 to conduct less readily and the voltage at the junction of CR 27 and C-R 32 rises to provide a drive to the base of C-Q 7, causing C-0 7 to conduct and further to reduce the drive through C-R 28 to C-Q 8. These combined actions act quickly to drive GO 7 into conduction and to cut off CO 8. Each successive negative going pulse will similarly change the state of conduction and of nonconduction of the C-Q 7, C-Q 8 combination. When C-0 8 conducts, the voltage at the terminal 18 (FF-1) approaches 6 v., since C-R 32 is chosen so that its resistance is very much greater than the internal resistance of C-Q 8. At the the same time, the voltage at terminal 23 (FF-1) approaches the +22 volt source because the current OR 30 is very small due to th e high resistance of C-Q 7 in its nonconducting condition. FF] is always opposite in value to FF-l. Thus when FF-l approaches +22 volts, FF-l approaches -6 volts and when IT-l a p p oaches 6 volts, FF-l approaches +22 volts. FF-2 and FF-Z; FF-3 and FF-3 are similar sets. A brief examination of FIG. 3 shows that CO 6 and GO 5 are associated components; and GO 4 and C-Q 3 are associated components are identical counterparts of C0 8 and-C-Q 7 and its associated components.

When C-Q 8 changes from a nonconducting to a conducting condition the voltage at the junction of C-R 32 and GO 8 changes rapidly from approximately +22 volts to approximately -6 volts. This negative going voltage applied to the junction of C-C 9 and C-C 10, changes the conducting and nonconducting conditions of GO 6 and C-Q 5. When C-Q 6 changes from nonconduction to conduction, the negative going voltage produced at the collector of GO 6 changes the conducting and nonconducting conditions C-Q 4 and GO 3. If it is assumed that GO 8, C-Q 6 and C-0 4 are all conducting, then the outputs at terminals 18, 19 and 20 will be very low and the outputs at terminals 23, 22 and 21 will be high. Low voltage is designated as 0 and high voltage as I (seen FIG. 3A), MIN. GREEN 1 is 0, 0, 0,. The first negative pulse applied to the junction of C-C 13 and C-C 12 acts on GO 7 and O0 8 so that the output at 18 is high and the output at 23 is low. The first negative pulse thus causes the condition listed as MIN. GREEN II (1, 0, 0,). The next negative pulse to CC 12, C-C 13 causes the negative pulse to appear at the collector of Gt) 8 which drives GO 5 into conduction. This condition is listed as REST I (0, 1,0,). It will be seen that successive negative pulses at the C-C 12, C-C 13 junction produce the sequence of counter outputs listed in FIG. 3A.

It will be noted that the binary counter has eight positions. The traffic controller herein described requires only six positions. The conversion of an eight-counter into a six-counter is well known and is usually done by the use of feed back circuits requiring additional components. The method used in this invention involves an actual reduction of components. the MIN. GREEN is divided into two sections MIN. GREEN I and MIN. GREEN II each of which is timed for half the period required for MIN. GREEN, ,using the same timing element twice. The REST positions, untimed, is converted into two positions in a similar manner. It is apparent that this method can be utilized for any control device in which the control positions (number of) is less than the exact number of positions of the counter, with a consequent increase in dependability'and economy of components.

When energy is first applied to the counter, it is important for safe traffic control that the counter and signals assume a definite predetermined position. The +22 voltage source is directed through C-R 18 to CO 7 through OR 30, to C-0 5 through C-R 23, and to CO 3 through C-R 12. Similarly, the +22 voltage source is directed through OR 17 to C-Q 8 through C-R 32, to C-Q 6 through C-R 25 and to C-Q 4 through C-QR 14. Capacitor C-C 3 delays the application of the voltage through C-R 17. This action delays the application of the drive currents to the bases of O0 7, C-Q 5 and C-Q 3. Thus, at turn on, transistors 00 8, CO 6 and O0 4 will conduct more readily than C- 7, C-0 and C-() 3, placing the counter in the MIN. GREEn l condition. It will be seen that any turn on counter position can be predetermined by the connection of the collector resistors to either OR 17 or C-R I8.

Transistor (-0 2 is turned on from the +22 sourcethrough C-R I7 and OR 2 to the base of C-0 2. The -6 voltage applied to the base of C-Q 1 through C-R 4 prevents C-O l'fr'om conducting. The voltage at the junction of C-C Zand C-R 7 is consequently close to the +22 volt source. Transistor CO. 1 can be driven into conduction by a positive pulse applied to it base. The positive pulse may be applied to terminal and coupled. to the base through C-C 7 and GD 1 or-it may be applied by grounding and then ungrounding the terminal l2.Tl1e:- resulting'positive going pulse is coupled to the base of C-Q'l' by means of C-C 8 and C-D 2. Resistors C-R 5-and CR 6 are used as discharge paths for C-C 7 and CC 8 respectively. The change of C-Q 1 from the nonconducting to the conducting state causes the voltage at the collector of C-Q,1 fall rapidly. This action is coupled through C-.C 2 to the base of C-Q 2, turning off GO 2 until C C 2 becomes charged through C-R 2, whereupon if the positive goingpulse no longer exists at the outputs of GO 4 through G-Q 9 are applied to the transistors 0-0 1, 0-0 2, andG-Q 3. Transistor 6-0 9 drives GO 3 through GD 26 and GR 8; 0-0 9 drives 0-0 2 through G-D 27 and GR 5. In a similar fashion, 6-0 8 drives 6-0 2 through 6D and G-R 8; and drives G-Q 3v through G-D 24 and G-R S. The output ofG-Q 7 drives G-Q 3 through G-D 23 and G-R 8. The output of 0-0 5 drives 6-0 1 through 6D 3 and GR 2; and. drives 6-0 2 through G-D 4-ancl G-R 5. Resistors G-R l, G-R 4 and G-R 7 connected to the 6 volt source provide positive turn off of G 0 1, 0-02, and 6-0 3 when turnon drive is not present. Relay coil K 1 (see FIG. 6, relay panel) is connected to the +27 volt source, to terminal 28 and thence to the collector of 6-0 3. Relay Kv 1 will be energized whenever G-Q v 3 is caused to conductby the positive signal voltage through G -D 26, 6-D 23, or GD 25:. Relay coil K 2 is similarly energized by means of 6-0, 2, andirelay coil K3 is energized by means ofG-Q 1. Thus the sequential andselective operation of the relays and the signal lights is controlled by the relay drive transistors, GO 3, G-Q 2 and 0-0 1 which are actuated by the gate amplifiers, which inturn are controlled'by the counter-circuit. The following table lists the operation of the relay drive transistors, the relays and the signal lights.

base of C-0 1, GO 2 will turn on once more. When C-Q 1.

turns on, a negative step results at the collector of GO 1. This negative step is coupled to CC 13 and C-C 12 to operate the counter. Simultaneosuly, a positive step results at the collector of C-0 2. This positive step isfed toterminal 11 and is usedto discharge the timer capacitor T-C 4 (FIG. 2.).

The outputs of the counter( FIG. 3) are connected to ter' minals 18, 19, 20, 21, 22 and 23, of the. code gates (see FIG. 4). Transistors 0-0 4, (3-0 5, 6-0 6, 0-0 7, G-() 8 and 0-0 9 are emitter followers which are driven from the +22 volt source through G-R 3, GR 6, G-R 9, G-R 10, G-R 11, G-R 12 respectively. The bases of the transistomare stabilized at .+l7

volts by the connection of the diodes G-D 33. It will be seen that the drive from G-Q 4 will not be present if either terminals 18, 19 and 20is at a potentialclose to the 6 volt source; that is, 0-0 4 will conduct only if the cathodes of GD 5, GD 6 and 6-0 7 are all at a potential sufficiently high so that there can be a current path from the +22. volt source through G-R 3 through the base emitter circuit of 6-0 4. A similar analysis will show that: 6-0 5 conducts when the cathodes of G-D 11, 0-D 9 and 0-D 10 are positive; this occurs when terminals 23, 19 and 20 are positive. Theresult is a voltage available at terminal 16.

The condition under which G-Q 6, G-Q 7, GO 8 and 0-0 9 conduct may be readily adduced. The following table summarizes the results:

In addition to the voltage outputs at the terminals-listed, the

The outputs available at 24, 14, 25, 26, 16 and 27' are applied to the control panel (see FIG. 5). When the counter is in position 1 or 2, the voltage at terminal 24 illuminates indicator signal P-DS 3 which isconnected to the common ground terminal. The voltage is'also led to terminal 17 through P-R 8, variable resistor P-R 9 and diode PD 3. Terminal 17 is similarly energized from terminal 25 through PR-S, variable resistor PR-6 and diode' PD-2. Terminal 25 will be energized from terminals 26, 16 and 27 as the counter assumes successive positions.

The voltage at terminal 17 is utilized to charge the timing capacitor-T-C 4 (see FIG. 2). Transistors T-Q G and T-Q. 5. form a two-stage direct coupled amplifier. The emitters are elevated from groundby means of the voltage divider formed by T-R 19, temperature compensating diodes T-D 11 and T-D 12 and variableresistorT-R 20. Transistor TO 6 is biased so that it is essentially nonconducting. Transistor T-Q 5 is driven into conduction from the +17 volt. source through T-R l8 and T-R 16. As a result the voltage at terminal 10 is slightly above that at the emitter of T-Q' 5; The voltage at terminal 17 obrained through adjustable resistances P-R 9, P-R 6, lP-R 3, B-R 18 or P-R ll5rises slowly when applied to the capacitor T-C 4. when the voltage rises to a value sufficiently high (as set by T- R 20) T-Q 6 is driven into conduction through diodes TD 7 and T-D 10.- When T-Q 6 is driven into-conduction, the voltage at the junction ofT-R 18 and T-R 16 goes down; this action deprives the baseof transistor T-Q 5 of the drive formerly available through T-R l6; and T-Q 5 no longer conducts. Thus a positive going step is produced at terminal 10.

This positive going step is applied to the monostable multivibrator formed by C-Q l andC-Q 2 (FIG. 3). The result is, as previously described, that the counter moves one position. The positive going pulse at terminal 11 is directed to the base of T-Q 4 through diode'T-D 9 and TR 12. This pulse drives T- Q' 4 into conduction, discharging T-C 4 through diode T-D 7 and also discharging T-C 2 through T-D 6.

Reference to FIG. 5 showsthat voltage is available. at terminal 17 except when the counter is in the REST position. The time for each of the positions, except REST, is determined by the setting of the variable resistors such as P-R 9, P-R 6, et cetera, and TC 6. The counter is taken out of the REST position by a combination of actions. These actions include a call from a pedestrian and a ground from the coordination control.

Transistors T-Q I and T-Q 2 (see FIG. 2) form a bistable multivibrator in which either of the transistors is conducting while the other one is nonconducting. When the counter reaches the WALK position, a positive signal is applied to terminal I6. This voltage is applied to the base of T-Q 1 through diode T-D l and resistor T-R 1, driving T-Q i into conduction. After the WALK period is concluded, an actuation of the pedestrian pushbutton places a ground at the junction of T-R 9 and TR 2. The voltage divider composed of T-R 9, T-R 2 and T- 15 is designed so that the voltage at the junction of T- R 2 and T-R 15 is normally positive. Grounding of the pushbutton causes the voltage at the junction of T-R 2 and T-R 15 to reach a negative value. This negative is transmitted by T-D 2 to the base of "IQ l, causing T-Q l to stop conducting. Transistor T-Q 2 is driven into conduction from the +22 volt source through T-R 3 and T-R 6 to the base of T-Q 2. With T- Q 2 nonconducting, the voltage at the collector of T-Q 1; approaches the +22 volt value and is applied to the cathode of T- D 3.

Transistor T-Q 3 is driven into conduction by means of the +22 volts through T-R 7 and as a consequence the voltage at the collector of T-Q 3 is low. Grounding the coordination control terminal grounds the base of T 3, removing the drive from T-Q 3, causing it to become nonconducting, thus raising the cathode of T-D 5 to a value approaching the source voltage. When the counter reaches the REST "position, the cathode of T-D Sis positive. A voltage is applied from the +22 volt source through T-R I0 and T-R 11 to charge T-C 2. The drive through T-R 11 operates T-Q 6 through T-D 6 and T-D 10 when T-C 2 is charged. The value of T-C 2 is chosen so that in combination with T-R 10 and T-R 31 it has a relatively small time constant. Thus as soon as the REST position is reached, the counter is moved to the next position provided there is a CALL registered and the coordination control is closed.

When the recall switch P-SW (FIG. 5) is closed, ,the REST position voltage, terminal 14, is fed to terminal 13 through P- R 11 to drive T-Q 2 into conduction. Thus a memory signal is registered during each cycle and the controller will recycle continually without the need for a pedestrian actuation.

The manual switch (see FIG. 2) is shown in the off position; when placed in the on position, a positive voltage is applied to the base of T-Q through T-D S and T-R 12. This turns on T- Q 4 and prevents T-C 4 or T-C 2 from charging; there will be no timed control of the counter. The operation of the manual control places a ground on terminal :2. This ground is applied to C-R 16 (FIG. 3) dropping the voltage at the junction ofC-R 16 and C-R 15. When the manual control is released, the voltage rises again and sends a positive pulse through C-C 8 and C-D 2 to C-Q 1. This action causes the counter to be pulsed into the next position.

While FIG. 6 shows the use of electromagnetic relays as output devices, these relays may readily be replaced by a combination of solid-state elements now commercially available.

It should be noted that the use of the two capacitors T-C 2 and T-C 4 (see FIG. 2) are both connected to enable controlled operation of the transistor amplifier T-Q 6. In practice, the value of T-C 2 is several magnitudes smaller than T-C 4, thus enabling an extremely wide divergence ofperiods without reducing the charging resistor T-R 11 to too small a value for practical purposes, or increasing the charging resistors P-R 9 to too large a value for practical purposes in operating the amplifier T-Q 6.

In order to avoid interfering unduly with vehicular traffic, a coordinating control signal may be introduced by momentarily grounding the base of T-Q 3, causing it to nonconduct and permitting the voltage at the cathode of T-D 4 to rise to +22 volts source value. Thejunction of T-D 5, T-D 3, T-D 4 and T- R 10 will be at ground potential unless the controller is at REST, and the bistable multivibrator is set so that T-Q l is not conducting, and a coordinating signal is received so that T-Q 3 does not conduct. When all these conditions are met, the current can flow through T-R III to charge T-C 2, to operate T-D l0 and consequently move the countcrout of the REST position.

It will be recognized that a permanent ground connected to the coordinating terminal enables the controller to respond to change the signals immediately upon reaching the REST position.

The application of traffic controls of the type herein described requires that the cyclical characteristic is variable as a result of variations in pedestrian traffic demands and in addition it is necessary that the termination of the right-of-way for the vehicles be controllable so that the moment of the termination can be coordinated, either simultaneously or at specific time spacing with other traffic controllers. The use of the transistors T-Q i and T-Q 2 connected as a bistable multivibrator and the use of the resistor network T-R 9, T-R 2 and T-R 15 connected between the +22 vo lt and the 6 y9It source permits a negative pulse to appear at T-Q 1 through diode T-D 2 when the junction of T-R 9 and T-R 2 is grounded by means of pedestrian action of the push button. It will be seen that the accidental or malfunctional grounding of the connections to the pushbutton will also act to introduce a call to the bistable multivibrator. Thus a ground will not cause malfunction of the controller but will cause cyclical operation.

In traffic control systems, it is frequently necessary to provide for a specific number of output conditions which do not correspond to the binary counter positions. In this invention, for example, the binary counter shown in FIG. 3, having three stages, has an output possibility of eight distinct conditions. The controller application, however, requires but six distinct positions as listed in the period column of FIG. 3A. There are various schemes to connect binary counters into fewer position counters, all of which require additional electronic components for the required forcing feedback signals. The present invention discloses a way not only to avoid this forcing feedback method and its attendant components, but to reduce still further the number of components needed. Other advantages are also evident in the reduction of the variable resistor value while still obtaining a long timing period. It will be seen in FIG. 4 that the gate controlling 6-0 4 is composed of diodes GD 5, 6-D 6 and G-D 7, in turn controlled by the counter outputs FF 1, FF 2, and FF 3. Similarly, G-Q 5, 6-0 6 and 0-0 7 are controlled by gates each requiring an output from all three stages of the binary counter. Transistor G-Q 9, however, is controlled from only two stages of the counter, namely, FF 2 and F3. Thus, G-Q 9 will be energized regardless of the position of the first stage of the counter, and consequently will be energized in two successive counter positions. The output of 0-0 9, fed to terminal 24, is in turn fed to the timing capacitor T-C 4 (see FIG. 2) through P-R 8, P-R 9 and P-D 3 (see FIG. 5). The timing resistor P-R 9 is used in two successive counter positions. The total timing for these two positions represents the timing required for the MIN. GREEN. Not only have the feedback elements been eliminated to make the binary eight into a six position, but in addition, the gating elements have been reduced as described. The principal described need not be limited to two successive counter positions but may also be extended to four positions, eight positions or N" positions if a control device utilizing a binary counter must have its effective number of positions reduced. For example, in a four-stage counter the number of counter positions will be 16. If only 13 conditions are to be utilized, one of the positions may be repeated four times by removing the gating elements such as diodes from control of the first and second stages of the counter. As a generality, if it is desired to utilize successive counter positions in one control period, the condition is readily created for 2 positions where the gating elements for one of the output devices is removed from the first, second, third---- to the N" stages of the counter output.

Although I have described and illustrated the preferred form of the invention, it is understood that variations in the diagram and in the elements and in other minor ways without departing from the spirit and scope of the invention and there fore I do not limit myself to the precise construction herein disclosed andl reserve the right to all changes and modifications coming within the scope of the invention as defined in any of the appended claims.

lclaim:

1. In a traffic controller for establishing a predetermined number of traffic flow conditions apparatus comprising:

a binary counter having a group of cascaded stages and capable of assuming a plurality of counts greater than said predetermined number, the first of said stages being advanced only in response to an input signal on its input terminal to advance the count in said counter once for each input signal applied on said input terminal with the remaining ones of said stages being advanced only in response to a signal from the preceding stage,

means for repetitively applying signals to said input terminal to thereby advance said count,

logical circuit means coupled to said binary counter and responsive only to the count in said counter for sequentially establishing said predetermined number of traffic flow conditions.

said logical circuit means including means for establishing at least one of said traffic flow conditions for at least two successive ones of said counts by responding only to the states of said remaining ones of said counter stages independently of the state of said first stage 2. Apparatus in accordance with claim 1 and further comprising timing circuit means for controlling the duration in which said counter means resides with at least said at least two successive ones of said counts.

3. Apparatus in accordance with claim 1 wherein said predetermined number is six:

said binary counter is a three-stage counter with said plurality being eight,

and said logical circuit means includes means responsive to binary 000 and 001 for establishing the first of said traffic flow conditions and means responsive to binary 010 and OH for establishing the second of said traffic flow conditions. 

1. In a traffic controller for establishing a predetermined number of traffic flow conditions apparatus comprising: a binary counter having a group of cascaded stages and capable of assuming a plurality of counts greater than said predetermined number, the first of said stages being advanced only in response to an input signal on its input terminal to advance the count in said counter once for each input signal applied on said input terminal with the remaining ones of said stages being advanced only in response to a signal from the preceding stage, means for repetitively applying signals to said input terminal to thereby advance said count, logical circuit means coupled to said binary counter and responsive only to the count in said counter for sequentially establishing said predetermined number of traffic flow conditions, said logical circuit means including means for establishing at least one of said traffic flow conditions for at least two successive ones of said counts by responding only to the states of said remaining ones of said counter stages independently of the state of said first stage.
 2. Apparatus in accordance with claim 1 and further comprising timing circuit means for controlling the duration in which said counter means resides with at least said at least two successive ones of said counts.
 3. Apparatus in accordance with claim 1 wherein said predetermined number is six: said binary counter is a three-stage counter with said plurality being eight, and said logical circuit means includes means responsive to binary 000 and 001 for establishing the first of said traffic flow conditions and means responsive to binary 010 and 011 for establishing the second of said traffic flow conditions. 